You see, my colleague has been toiling away on the design in between paid work which has been, unfortunately, quite sporadic for him lately. I knew he'd made some headway with the layout, but it came as a complete surprise when he presented me with the gerbers this afternoon!
Needless to say, I have a lot of catching up to do. I had started the HDL months ago, but that had languished on the back-burner whilst Lode Runner took all my spare time. Now I need to crank up Quartus again and finish it off, to ensure that the connectivity (eg. pin mapping) is correct and that the hardware design is adequate for the intended functionality.
And before I send out the board for manufacture, I also want to do a preliminary draft of the schematic for the flash cartridge, for the same reasons outlined above. And of course I need to do a thorough design review of the current PCB, so there's a fast growing pile of work on my plate.
Once manufactured, I'll be in a position to run the analyser functionality through its paces. The point was to obtain detailed bus timing diagrams for both CHA and PRG cartridge buses, via the Quartus SignalTap tool - information that will be invaluable for the FPGA implementation of the motherboard. The programmer functionality will only be useful when the next PCB - the flash cart - has been finished.
My final comment on the subject for this entry is that my dreams of hand-assembling the few (4?) boards that I will get loaded have been dashed by my colleague's rather... comprehensive... design practices. Suffice it to say, industrial strength power supplies and I/O protection are included as standard. I guess that means the production version won't require much in the way of a re-spin.
And a note on the possible Neo Geo port of Lode Runner I mentioned in the last entry; instead of producing a 68K translation I wrote a C version which should be (more) readily portable to any 16-bit or newer system. Progress here.
The next few updates on the analyser/programmer PCB should be a lot more frequent now!