Sunday, 31 August 2014

August Update

I've finished the Quartus project pin assignments for both the CHA and PRG projects. I've also built the analyser configuration for each of those projects and they appear to build without issue. Nothing exciting here as each pin is configured as I/O and tri-stated so that the SignalTap analyser can be enabled. I've also confirmed there's enough memory on the device (EP3C16) for a decent trace.

The programmer function build for the CHA project includes a NIOS with sufficient PIO to drive the three (3) buses and - in theory - the FLASH control pins. I've hooked up the former, but not the latter. That's my next task on the list, before I attempt to write the programmer function software.

Once that's done I'll repeat the exercise for the PRG project, and we should be (almost) good to go for manufacture of the programmer/analyser PCB - it would be prudent to do further research on the known bank-switching and protection mechanisms in newer cartridges before committing the design to manufacture.

The programmer/analyser should (incidentally) also have the capability to operate as an MVS->AES converter board. No doubt there's some tweaking to be done in the sprite data serialisation, given the technical issues with most of the commercial converter boards. It's something I'll have to tackle on the flash cartridge eventually, as it will of course operate in both MVS & AES systems. I do not, however, have any intention of producing commercial converter boards; I'll leave that to those who have already done so. I have no desire to encroach on existing markets.

Realistically, I'm hoping to send out the PCB before the end of September.

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